The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, polysilicon gates have been replaced by metal gates in an effort to improve device performance with decreased feature size. However, there are challenges associated with forming contact features on metal gates during device fabrication. In one example, interface between a contact feature and a metal gate can experience high resistance that is difficult to control due to reduced feature size. One possible improvement is to reduce resistance between the contact feature and the metal gate by growing a low resistive conductive layer therebetween. Meanwhile, there is a need to maintain electrical property stability of the metal gate without being interfered by the overlaid low resistive conductive layer. Therefore, further improvements in this area are desired.